ROHS compliant ML605 Base Board including the XC6VLX240T-1FFG1156 FPGA FPGA Design Software A full-seat of Xilinx ISE Design Suite: Logic Edition Device-Locked to Virtex-6 LX240T FPGA. Targeted Reference Designs PCI Express Gen2 (x8) PCI Express Gen 1 (x8) Base Reference Design DDR3 Memory Interface IBERT Multiboot Getting Started Demonstration documentation Hardware Setup Guide Getting Started Guide Hardware User Guide Reference Design User Guide Board Design Files - Schematics/Gerbers/BOM Cables & Power Supply 12V Universal Power Supply Two USB Cables One Ethernet Cable DVI To VGA Adapter Key Features FPGA: XC6VLX240T-1FFG1156? configuration Onboard configuration circuitry (USB to JTAG) 128MB Platform Flash XL 32MB Parallel (BPI) Flash system ACE 2G Compact FLASH (CF) Card Communications and Networking 10/100/1000 Tri-Speed Ethernet (GMII, RGMII, SGMII, MII) SFP transceiver connector GTX port (TX, RX) with four SMA connectors? USB To UART Bridge USB Host Port and USB Peripheral Port PCI Express Gen 1 and Gen2 x8 Memory DDR3 SO-DIMM (512 MB) BPI Linear Flash (32 MB) (Also available for configuration) IIC EEPROM (8 Kb) Clocking 200 MHz Oscillator (Differential) Oscillator socket (Single-Ended) SMA Connectors for external clock (Differential) GTX Reference Clock port with 2 SMA connectors? Input/Output and Expansion Ports 16x2 LCD character display DVI Output system Monitor User Push buttons (5), DIP switches (13), LEDs (13) User GPIO with two SMA connectors Two FMC Expansion Ports High Pin count (HPC) Eight GTX Transceivers 160 selectIOs Low Pin count (LPC) One GTX Transceiver 68 selectIOs Power 12V wall adapter or ATX Voltage and Current measurement capability of 2.5V, 1.5V, and 1.2V, 1.0V supplies
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